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PD - 94782
IRF3704ZCS IRF3704ZCL
Applications l High Frequency Synchronous Buck Converters for Computer Processor Power
HEXFET(R) Power MOSFET
VDSS RDS(on) max
20V 7.9m:
Qg
8.7nC
Benefits l Low RDS(on) at 4.5V VGS l Ultra-Low Gate Impedance l Fully Characterized Avalanche Voltage and Current
D2Pak IRF3704ZCS
TO-262 IRF3704ZCL
Absolute Maximum Ratings
Parameter
VDS VGS ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C PD @TC = 100C TJ TSTG Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current
Max.
20 20 67 47
Units
V A
c
g g
260 57 28 0.38 -55 to + 175 W/C C W
Maximum Power Dissipation Maximum Power Dissipation Linear Derating Factor Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds
300 (1.6mm from case)
Thermal Resistance
Parameter
RJC RJA Junction-to-Case Junction-to-Ambient (PCB Mount)
Typ.
Max.
2.65 40
Units
C/W
f
--- ---
Notes through are on page 11
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1
9/15/03
IRF3704ZCS/L
Static @ TJ = 25C (unless otherwise specified)
Parameter
BVDSS VDSS/TJ RDS(on) VGS(th) VGS(th)/TJ IDSS IGSS gfs Qg Qgs1 Qgs2 Qgd Qgodr Qsw Qoss td(on) tr td(off) tf Ciss Coss Crss Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Gate Threshold Voltage Coefficient Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Forward Transconductance Total Gate Charge Pre-Vth Gate-to-Source Charge Post-Vth Gate-to-Source Charge Gate-to-Drain Charge Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) Output Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance
Min. Typ. Max. Units
20 --- --- --- 1.65 --- --- --- --- --- 48 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 0.014 6.3 8.9 2.1 -5.6 --- --- --- --- --- 8.7 2.9 1.1 2.3 2.4 3.4 5.6 8.9 38 11 4.2 1220 390 190 --- --- 7.9 11.1 2.55 --- 1.0 150 100 -100 --- 13 --- --- --- --- --- --- --- --- --- --- --- --- --- pF VGS = 0V VDS = 10V ns nC nC VDS = 10V VGS = 4.5V ID = 17A S nA V mV/C A V
Conditions
VGS = 0V, ID = 250A
V/C Reference to 25C, ID = 1mA m VGS = 10V, ID = 21A VGS = 4.5V, ID = 17A
e e
VDS = VGS, ID = 250A VDS = 16V, VGS = 0V VDS = 16V, VGS = 0V, TJ = 125C VGS = 20V VGS = -20V VDS = 10V, ID = 17A
See Fig. 16 VDS = 10V, VGS = 0V VDD = 10V, VGS = 4.5V ID = 17A Clamped Inductive Load
e
= 1.0MHz
Avalanche Characteristics
EAS IAR EAR Parameter Single Pulse Avalanche Energyd Avalanche CurrentA Repetitive Avalanche Energy Typ. --- --- --- Max. 36 17 5.7 Units mJ A mJ
--- --- --- --- --- --- --- --- 11 2.3
Diode Characteristics
Parameter
IS ISM VSD trr Qrr Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge
Min. Typ. Max. Units
67
g
Conditions
MOSFET symbol
D
A 260 1.0 17 3.5 V ns nC
showing the integral reverse
G S
p-n junction diode. TJ = 25C, IS = 17A, VGS = 0V TJ = 25C, IF = 17A, VDD = 10V di/dt = 100A/s
e
e
2
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IRF3704ZCS/L
1000
VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V TOP
1000
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
100
100
VGS 10V 9.0V 7.0V 5.0V 4.5V 4.0V 3.5V BOTTOM 3.0V TOP
3.0V
10
10
3.0V
60s PULSE WIDTH Tj = 25C
1 0.1 1 10
60s PULSE WIDTH Tj = 175C
1 0.1 1 10
VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
1000.0
2.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current ()
ID = 42A VGS = 10V
T J = 25C T J = 175C
1.5
100.0
1.0
VDS = 10V 60s PULSE WIDTH
10.0 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRF3704ZCS/L
10000
12
VGS, Gate-to-Source Voltage (V)
VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
ID= 17A 10 8 6 4 2 0
VDS= 16V VDS= 10V
C, Capacitance (pF)
1000
Ciss
Coss
Crss
100 1 10 100
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
1000.0
1000 OPERATION IN THIS AREA LIMITED BY R DS(on)
100.0 T J = 175C 10.0
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
100
100sec 10 1msec 10msec 1 10 100
1.0
T J = 25C VGS = 0V
0.1 0.0 0.5 1.0 1.5 2.0 VSD, Source-toDrain Voltage (V)
1
Tc = 25C Tj = 175C Single Pulse 0
VDS , Drain-toSource Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
4
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IRF3704ZCS/L
70 LIMITED BY PACKAGE 60
ID , Drain Current (A)
2.6
VGS(th) Gate threshold Voltage (V)
2.2
50 40 30 20 10 0 25 50 75 100 125 150 175 T C , Case Temperature (C)
ID = 250A
1.8
1.4
1.0
0.6 -75 -50 -25 0 25 50 75 100 125 150 175 200
T J , Temperature ( C )
Fig 9. Maximum Drain Current vs. Case Temperature
Fig 10. Threshold Voltage vs. Temperature
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10
0.1
0.05 0.02 0.01
J J 1
R1 R1 2
R2 R2
R3 R3 3 C 3
Ri (C/W) i (sec) 0.920 0.000139 0.194 0.538 0.000602 0.001567
1
2
0.01
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci= i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01
0.001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRF3704ZCS/L
15V
140
EAS, Single Pulse Avalanche Energy (mJ)
VDS
L
DRIVER
120 100 80 60 40 20 0 25 50 75 100
ID 5.6A 8.5A BOTTOM 17A
TOP
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS tp
125
150
175
Starting T J, Junction Temperature (C)
Fig 12c. Maximum Avalanche Energy vs. Drain Current
I AS
LD VDS
Fig 12b. Unclamped Inductive Waveforms
+
VDD D.U.T VGS Pulse Width < 1s Duty Factor < 0.1%
50K 12V .2F .3F
Current Regulator Same Type as D.U.T.
Fig 14a. Switching Time Test Circuit
D.U.T. + V - DS
VDS
90%
VGS
3mA
10%
IG ID
Current Sampling Resistors
VGS
td(on) tr td(off) tf
Fig 13. Gate Charge Test Circuit
Fig 14b. Switching Time Waveforms
6
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IRF3704ZCS/L
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
Id Vds Vgs
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 16. Gate Charge Waveform
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IRF3704ZCS/L
Power MOSFET Selection for Non-Isolated DC/DC Converters
Control FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. Power losses in the control switch Q1 are given by; Synchronous FET The power loss equation for Q2 is approximated by;
* P =P loss conduction + P drive + P output
P = Irms x Rds(on) loss
+ (Qg x Vg x f )
(
2
)
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
Q + oss x Vin x f + (Qrr x Vin x f ) 2
*dissipated primarily in Q1.
Ploss = (Irms x Rds(on ) )
2
Qgs 2 Qgd +Ix x Vin x f + I x x Vin x ig ig + (Qg x Vg x f ) + Qoss x Vin x f 2
f
This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Qgs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage.
For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs' susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on.
Figure A: Qoss Characteristic
8
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IRF3704ZCS/L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
D2Pak Part Marking Information
T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" INT ERNAT IONAL RECT IFIER LOGO AS S EMBLY LOT CODE PART NUMBER F530S DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L
For GB Production
T HIS IS AN IRF530S WIT H LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN T HE AS S EMBLY LINE "L" INT ERNAT IONAL RECT IFIER LOGO LOT CODE PART NUMBER F530S DAT E CODE
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IRF3704ZCS/L
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
IGBT 1- GATE 2- COLLECTOR
TO-262 Part Marking Information
EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS SEMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" INT ERNAT IONAL RECTIFIER LOGO AS SEMBLY LOT CODE PART NUMBER
DAT E CODE YEAR 7 = 1997 WEEK 19 LINE C
10
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IRF3704ZCS/L
D2Pak Tape & Reel Information
TRR
1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153)
1.60 (.063) 1.50 (.059) 0.368 (.0145) 0.342 (.0135)
FEED DIRECTION 1.85 (.073)
1.65 (.065)
11.60 (.457) 11.40 (.449)
15.42 (.609) 15.22 (.601)
24.30 (.957) 23.90 (.941)
TRL
10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 16.10 (.634) 15.90 (.626) 4.72 (.136) 4.52 (.178)
FEED DIRECTION
13.50 (.532) 12.80 (.504)
27.40 (1.079) 23.90 (.941)
4
330.00 (14.173) MAX.
60.00 (2.362) MIN.
NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
26.40 (1.039) 24.40 (.961) 3
30.40 (1.197) MAX. 4
Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25C, L = 0.25mH, RG = 25, IAS = 17A. Pulse width 400s; duty cycle 2%.
This is applied to D2Pak, when mounted on 1" square PCB (FR4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 42A.
Data and specifications subject to change without notice. This product has been designed and qualified for the Consumer market. Qualification Standards can be found on IR's Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 09/03
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